The transition from aluminum to copper in integrated circuit (IC) fabrication required a change in process “architecture” (to damascene and dual-damascene) as well as a whole new set of process technologies. One process step used in producing copper damascene circuits is the formation of a “seed-” or “strike-” layer, which is then used as a base layer onto which copper is electroplated (“electrofill”). The seed layer carries the electrical plating current from the edge region of the wafer (where electrical contact is made) to all trenches and via structures located across the wafer surface. The seed film is typically a thin conductive copper layer. It is separated from the insulating silicon dioxide or other dielectric by a barrier layer. The seed layer deposition process should yield a layer which has good overall adhesion, excellent step coverage (more particularly, conformal/continuous amounts of metal deposited onto the side-walls of an embedded structure), and minimal closure or “necking” of the top of the embedded feature.
Market trends of increasingly smaller features and alternative seeding processes drive the need for a capability to plate with a high degree of uniformity on increasingly thin seeded wafers. In the future, it is anticipated that the seed film may simply be composed of a plateable barrier film, such as ruthenium, or a bilayer of a very thin barrier and copper (deposited, for example, by an atomic layer deposition (ALD) or similar process). Such films present the engineer with an extreme terminal effect situation. For example, when driving a 3 amp total current uniformly into a 30 ohm per square ruthenium seed layer (a likely value for a 30-50 Å film) the resultant center to edge (radial) voltage drop in the metal will be over 2 volts. To effectively plate a large surface area, the plating tooling makes electrical contact to the conductive seed only in the edge region of the wafer substrate. There is no direct contact made to the central region of the substrate. Hence, for highly resistive seed layers, the potential at the edge of the layer is significantly greater than at the central region of the layer. Without appropriate means of resistance and voltage compensation, this large edge-to-center voltage drop could lead to an extremely non-uniform plating rate and non-uniform plating thickness distribution, primarily characterized by thicker plating at the wafer edge. This plating non-uniformity is radial non-uniformity, that is, uniformity variation along a radius of the circular wafer.
Another type of non-uniformity, which needs to be mitigated, is azimuthal non-uniformity. For clarity, we define azimuthal non-uniformity, using polar coordinates, as thickness variations exhibited at different angular positions on the workpiece at a fixed radial position from the wafer center, that is, a non-uniformity along a given circle or portion of a circle within the perimeter of the wafer. This type of non-uniformity can be present in electroplating applications, independently of radial non-uniformity, and in some applications may be the predominant type of non-uniformity that needs to be controlled. It often arises in through resist plating, where a major portion of the wafer is masked with a photoresist coating or similar plating-preventing layer, and the masked pattern of features or feature densities are not azimuthally uniform near the wafer edge. For example, in some cases there may be a technically required chord-region of missing pattern features near the notch of the wafer to allow for wafer numbering or handling. The radially and azimuthally variable plating rates inside missing region may cause chip die to be non-functional, therefore methods and apparatus for avoiding this situation are needed.
Electrochemical deposition is now poised to fill a commercial need for sophisticated packaging and multichip interconnection technologies known generally as wafer level packaging (WLP) and through silicon via (TSV) electrical connection technology. These technologies present their own very significant challenges.
These technologies require electroplating on a significantly larger size scale than damascene applications. Depending on the type and application of the packaging features (e.g. through chip connecting TSV, interconnection redistribution wiring, or chip to board or chip bonding, such as flip-chip pillars), plated features are usually, in current technology, greater than about 2 micrometers in diameter and typically are 5-100 micrometers in diameter (for example, pillars may be about 50 micrometers). For some on-chip structures such as power busses, the feature to be plated may be larger than 100 micrometers. The aspect ratios of the WLP features are typically about 2:1 (height to width) or lower, more typically 1:1 or lower, while TSV structures can have very high aspect ratios (e.g., in the neighborhood of about 10:1 or 20:1).
Given the relatively large amount of material to be deposited, not only feature size, but also plating speed differentiates WLP and TSV applications from damascene applications. For many WLP applications, plating must fill features at a rate of at least about 2 micrometers/minute, and typically at least about 4 micrometers/minute, and for some applications at least about 7 micrometers/minute. The actual rates will vary depending on the particular metal being deposited. But at these higher plating rate regimes, efficient mass transfer of metal ions in the electrolyte to the plating surface is very important. Higher plating rates present challenges with respect to uniformity of the electrodeposited layer.